Intel Sandy Bridge (microarchitecture)

Sandy Bridge is the codename for a processor microarchitecture that is being developed by Intel and is the planned successor to Nehalem. Intel started development of Sandy Bridge in 2006. Sandy Bridge uses the 32 nmmanufacturing methods from Westmere (formerly known as Nehalem-C) and applies it to the new Sandy Bridge microarchitecture^[1]. The former codename for this core was Gesher (means 'bridge' in Hebrew), but that codename was abandoned on 17 April 2007 because a political party in Israelis also named Gesher, as mentioned in Justin Rattner's keynote at IDFSpring 2007^[2]. Intel has stated that they "are evaluating options to adjust Sandy Bridge schedule to ensure sufficient Nehalem lifecycle," and so Sandy Bridge may be released later than originally planned.

Architecture

Sandy Bridge's specifications are reported to be as follows, according to a presentation made by Intel in December 2006: These specifications share similarities with the Core i9 processor.

• 4 GHz clock speed
• 4 to 8 cores
• Without SSE: 8 DP GFLOPS/core (2 DP FP/clock), 32-64 DP GFLOPS/processor.
• With SSE: 32 DP GFLOPS/core (8 DP FP/clock), 128-256 DP GFLOPS/processor.
• 64 KB L1 cache/core(32 KB L1 instruction and 32 KB L1 data cache per core), (3 clocks).
• 512 KB L2 cache/core, (9 clocks).
• 2-3 MB L3 cache/core (8-24 MB total) (33 clocks), most likely pooled and dynamically allocated among the cores.
• 64 bytes cache line width.
• 256 bytes/cycle Ring bus bandwidth. The ring bus connects the cores.
• 0-512 MB GDDR / fast DRAM.
• 64 GB/s GDDR / fast DRAM memory bandwidth.
• 17 GB/s memory bandwidth per QuickPath link with 50 ns latency.

According to some PC Watch articles:

• Sandy Bridge will be an evolutionary step from Core 2.
• Sandy Bridge will focus on power efficiency.
• Performance will be increased without a core size increase (similar to the Netburst to Core transition).
• The CPU core is scalable.
• Due to the small 32 nm process, the floating point unit is small compared to the rest of the core.
• Dynamic Turbo allows the CPU power to exceed the TDP value when the rest of the platform is relatively cool. The frequency gain can be up to 37% for one minute, and over 20% in most cases.
• Nehalem may stay at the server platform while Sandy Bridge is released for the mobile segments, which would split the markets into two CPU lines.
• Sandy Bridge's CPU and GPU are likely to be on one die (unlike the two-die approach of Nehalem).
• Because of the high-performing CPU and off-chip components, it may be necessary to improve bus interconnects. The internal bus is to be improved.
• The Sandy Bridge microarchitecture is also said to focus on the connections of the processor core.
• If the transition to 22 nm is difficult, then Sandy Bridge may go over three generations (Sandy Bridge, Ivy Bridge, and another Bridge) as opposed to two with Nehalem and Core 2.

The mobile Sandy Bridge version is expected to be released at the same time as the microarchitecture, which would mean a short 1-year life of mobile Nehalem. The platform chipset'snorthbridge is referred to as the 'Sandy Bridge System Agent' rather than 'MCH'.

Intel has said that Sandy Bridge will have new instructions called Advanced Vector Extensions (AVX). These instructions are an advanced form of SSE. The data path is widened from 128 bits to 256 bits, the two-operand instruction limit is increased to four operands, and advanced data rearrangement functions are included. AVX is suited for floating-point-intensive applications. Features of AVX include mask loads, data permutes, increased register efficiency and use of parallel loads, as well as smaller code size. The improvements of AVX will allow it to deliver up to double the peak FLOPS compared to before. Sandy Bridge will also have a new extensible VEX opcode prefix.